-------------------------------------------------------------------------------
-- Project    : stoch_add
-- File       : adder_config_ref.vhdl
-- Desc       : Configurable adder reference entity
-------------------------------------------------------------------------------
-- Author(s)  : Alberto Garcia-Ortiz¹ , Ardalan Najafi²  {¹agarcia,²ardalan}@item.uni-bremen.de
-- Company    : ITEM
-- Created    : 2016-10-04
-- Last update: 2019-08-16
-------------------------------------------------------------------------------
-- Copyright (c) 2016 
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;


entity adder_config_ref is

  generic (BW : natural);

  port (
    ci     : in  std_logic;
    da, db : in  std_logic_vector(BW-1 downto 0);
    dout   : out std_logic_vector(BW-1 downto 0);
    co     : out std_logic;
    ctr    : in  std_logic);

end entity adder_config_ref;


architecture str of adder_config_ref is
  signal c_s : std_logic_vector(0 downto 0);
  signal s_s : std_logic_vector(BW downto 0);
begin

  exact_mode : if crt = '0' generate
    c_s(0) <= ci;
    s_s    <= std_logic_vector(unsigned('0'&da)+unsigned('0'&db)+unsigned(c_s));

    dout <= s_s(BW-1 downto 0);
    co   <= s_s(BW);
  end generate;
  
end str;